Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.

Signed-off-by: Varun Wadekar <[email protected]>

diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 264749b68e0febd04b221dc5936d9af933a92111..2979b32dcd29ef1e90a5afe6dc30f2b160a3d468 100644 (file)
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -57,6 +57,7 @@
         */
 .macro cpu_init_common
 
+#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
        /* -------------------------------------------------------
         * Enable L2 and CPU ECTLR RW access from non-secure world
         * -------------------------------------------------------
@@ -65,6 +66,7 @@
        msr     actlr_el3, x0
        msr     actlr_el2, x0
        isb
+#endif
 
        /* --------------------------------
         * Enable the cycle count register

diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 41651d35e7d4f90cf31334f51e60af96f1a446c5..003b48960d0cf67f917ee4c09e119f589808114f 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -28,19 +28,22 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-TEGRA_BOOT_UART_BASE           := 0x70006000
+TEGRA_BOOT_UART_BASE                   := 0x70006000
 $(eval $(call add_define,TEGRA_BOOT_UART_BASE))
 
-TZDRAM_BASE                    := 0xFDC00000
+TZDRAM_BASE                            := 0xFDC00000
 $(eval $(call add_define,TZDRAM_BASE))
 
 ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT    := 1
 $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
 
-PLATFORM_CLUSTER_COUNT         := 2
+ENABLE_NS_L2_CPUECTRL_RW_ACCESS                := 1
+$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
+
+PLATFORM_CLUSTER_COUNT                 := 2
 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
 
-PLATFORM_MAX_CPUS_PER_CLUSTER  := 4
+PLATFORM_MAX_CPUS_PER_CLUSTER          := 4
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
 BL31_SOURCES           +=      ${SOC_DIR}/plat_psci_handlers.c \
@@ -49,3 +52,4 @@ BL31_SOURCES          +=      ${SOC_DIR}/plat_psci_handlers.c \
 
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319      :=      1
+